Jobid=05fb4943a865 (0.0202)
ph3Who are we? /h3pImagine being part of the dynamic journey at Qualinx – a startup born when three visionary PhD Engineers from TU Delft set out to revolutionize radio chip technology. At Qualinx, we’re on a mission to conquer the high‑power consumption challenges in Global Navigation Satellite Systems and IoT sensors. With a great team of over 40 individuals, scaling to 60 next year, hosting more than 18 nationalities, we’ve achieved the impossible – the world’s lowest power GNSS chipset. Now, we’re on the verge of unleashing our game‑changing digital RF technology product, ready to flood the market with millions of annual shipments. /ph3What Sets Us Apart /h3pJoining Qualinx isn’t just about a job; it’s about embracing high standards, and boldly navigating unexpected challenges. We thrive on collaboration, with a commitment to self‑improvement and product excellence. At Qualinx, you’re not just an employee; you’re an integral part of our exciting journey, contributing to the growth and success of a ground‑breaking solution. /ph3Job Description /h3pAs a Team Lead Digital ASIC Verification Engineer, you’ll play a role in shaping the future of our cutting‑edge technology. You will be responsible for the verification of our digital IP blocks and the simulation of chip‑level post‑layout within our upcoming SoCs. You will contribute to the circuit design for our next‑generation products. /pulliYou are responsible for ASIC verification, System Verilog, and UVM. /liliYou will be responsible for the simulation and verification of digital block implementation in RTL for various functions, including control state machine digital processing (DSP), and multiple clock domain interface management. /liliDuring your work at Qualinx you will be responsible for the post‑layout simulation of complex mixed‑signal SoC. /liliAs a Digital ASIC Verification engineer you will develop test benches and test cases for block‑level functional verification. /liliYou will work with our backend and implementation teams to address synthesis, timing, DFT issues for the ASIC implementation. /liliYou understand all design integration activities like Lint, CDC, synthesis ECO. /liliYou will define the verification and test plan, run regressions, reproduce, and debug functional and performance bugs. /liliYou are responsible for the verification of various IPs/Sub IPs integrated to the top level SoC. /liliLastly: you will have an understanding of the design synthesis and fix timing issues for the Physical Design team. /li /ulh3Requirements /h3pAt Qualinx, we seek a result‑driven Team Lead Digital Verification who thrives in an environment where proactive, can‑do attitudes are celebrated. Bring your passion and expertise and join us on this exciting venture. The ideal candidate should have: /pulliBachelor’s degree or higher in Electrical Engineering /lili10+ years of experience as an ASIC Verification Engineer. /liliA couple of years of experience as a team lead. /liliProficiency with EDA tools and design languages including Verilog. /liliExperience with standard EDA tools like Cadence and Mentor. /liliYou have experience in designing complex mixed‑signal products containing analog building blocks and microcontrollers. /liliYou have worked with RTL and ultra‑low‑power designs before. Good knowledge of digital design flow from architecture design to sign‑off. /liliYou understand synthesis, static timing analysis, and netlist verifications. /liliYou have some previous experience in digital backend flow for Floor Planning and Place Route (PNR). /liliYou understand digital DFT/ECO flow. /liliYou have strong programming and scripting skills:, C/C++, Tcl. /liliExperience in setting up Power Distribution architecture, power intent specification and validation methodology. /liliStrong knowledge of clock domain crossing (CDC) techniques. /liliUnderstanding of digital design flow including RTL simulation, logic synthesis, timing constraints, timing closure, STA, back annotation of parasitics, gate level simulation. /liliUnderstanding of ASIC test methodology such as scan insertion, memory BIST and test pattern generation. /liliStrong analytical, problem‑solving skills. /li /ulh3What's in it for you? /h3ulliGiven that we are a startup, we provide all our employees with Stock Appreciation Rights. You will be eligible to financially profit from Qualinx's success. /liliWe support you in your visa process if needed. /liliSaving for your pension: we provide an extra 2% of your monthly base salary. /lili25 vacation days based on a 40‑hour workweek. /liliWork in a beautiful and modern office with all the necessary equipment you need to deliver a great job. /liliEvery quarter we organize fantastic social events, where we celebrate the success of Qualinx by going out for a great meal, playing VR games, going bowling, etc. /liliAt Qualinx we invest in the development of our employees, we offer Quarterly Lunch Learn sessions to keep everyone who is interested up to speed. /li /ul /p #J-18808-Ljbffr
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