Jobid=b762b9849bf5 (0.0199)
Sr Layout Design Engineer
A fantastic opportunity for an experienced Layout Design Engineer to join a leading MEMS and Analog Semiconductor company, who offer the industry's most advanced and most reliable timing solutions.
As Sr. Layout Design Engineer you will lead top-level chip-planning and perform block-level custom layouts for CMOS and BiCMOS circuits.
Responsibilities will include reviewing, and coordinating work content performed by offshore layout designers, training junior layout engineers and offshore layout contractors to develop layout methodologies across the site, to achieve process and procedures for high layout quality.
Responsibilities:
- Requires remote interfacing with local and global design and layout teams in multiple design centres across different time zones
- Lead Top-level chip-planning and perform functional-block-level, block-level, sub-block level, leaf cell, standard cell custom layouts for CMOS and BiCMOS circuits
- Perform schematic-driven layout and design constraints
- Design die-area efficient layouts according to circuit designer requirements
- Perform block or top-level layout designs
- Perform floor-planning, power line planning, shielding, and device-matching layout
- Verify layouts. Pass DRC, LVS, and ERC
- Contribute to various chip-level routing and layout needs
- Perform chip level integration, verifications, and tape-out
- Support other projects as needed by management
- Train junior layout engineers and offshore layout contractors
- Contribute to develop common best practices and workflow across all sites
- Contribute to build process and procedures to achieve high layout quality.
Qualifications & Requirements:
- AA/AS Degree in Layout Design or related field or equivalent experience
- 10 years' experience with layout design for analog and full-custom digital blocks
- Experience TSMC 180nm, 65nm, 28nm and/or 22nm process technologies
- Proficient in using layout editing tools in the Cadence Virtuoso design environment
- Solid working knowledge of debugging DRC/LVS/ERC with Cadence PVS or Mentor Calibre
- Conceptual understanding of layout topics such as parasitic, matching, crosstalk, transistor layout dependent effects, latch-up, IR drop, electro migration (EM), and deep N-well and NTN isolation
- Strong capability of solving device matching, electro-migration, signal integrity and power distribution problems while meeting area constraints
- Experience in chip-level floor planning and analog block integration
- Experience chip level integration, verifications, and tape-out
- Ability to use productivity-enhancing tools and design scripts to further automate tasks is also desirable
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