Jobid=624601983278452147 (0.0149)
ppWe're partnered with a global semiconductor innovator developing high-performance timing and precision technologies used in advanced electronics across communications, data infrastructure, automotive, and industrial markets. /p pThey are now looking for a Senior Verification Engineer to join their team in Delft. /p pbPlease note this role is fully onsite. /b /p h3Responsibilities /h3 ul liDevelop SystemVerilog Real-Number Models (SV-RNM) for analog and mixed-signal circuits /li liCreate verification plans based on chip-level and block-level specifications /li liBuild and maintain UVM verification environments (scoreboards, monitors, sequencers, etc.) /li liDefine and implement SystemVerilog Assertions (SVA) /li liDevelop functional coverage models and covergroups /li liRun simulations, analyze results, and debug issues /li liReview verification outcomes to support tape-out sign-off /li liCollaborate closely with design, test, and verification stakeholders to ensure strong teamwork and effective knowledge sharing /li /ul h3Qualifications /h3 ul liMS (or BS) in Electrical/Computer Engineering or a related field with 5+ (or 8+) years of semiconductor verification experience /li liStrong written and verbal English communication skills /li liProficiency in SystemVerilog and object-oriented programming concepts /li liHands-on experience with UVM-based verification methodologies /li liProficiency with scripting languages such as Python or Perl /li liAbility to read analog schematics and practical experience with Cadence Virtuoso /li liWorking knowledge of digital design using Verilog /li liExperience collaborating with globally distributed mixed-signal, digital, and analog engineering teams /li liSelf-driven, with the ability to work independently and solve complex technical challenges /li /ul h3Desired Qualifications /h3 ul liExperience modeling analog functional behavior using SystemVerilog RNM, wreal (Verilog-AMS), or similar approaches /li liFamiliarity with UVM-AMS methodologies /li liStrong background in Formal Property Verification (FPV) /li liObject-oriented programming experience in C++ /li liExperience in analog mixed-signal verification /li liSolid understanding of analog design principles /li liKnowledge of synthesizable digital design /li liExperience verifying datapath designs, including filter implementations /li liProven ability to thrive in fast-paced, collaborative engineering environments /li liExcellent written and verbal communication skills /li /ul pBy applying to this role you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice /p /p #J-18808-Ljbffr
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