Jobid=bd52a2688efe (0.0143)
We're partnered with a global semiconductor innovator developing high-performance timing and precision technologies used in advanced electronics across communications, data infrastructure, automotive, and industrial markets.
They are now looking for a Senior Verification Engineer to join their team in Delft.
**Please note this role is fully onsite.**
Responsibilities
- Develop SystemVerilog Real-Number Models (SV-RNM) for analog and mixed-signal circuits
- Create verification plans based on chip-level and block-level specifications
- Build and maintain UVM verification environments (scoreboards, monitors, sequencers, etc.)
- Lead digital top-level verification using SystemVerilog
- Define and implement SystemVerilog Assertions (SVA)
- Develop functional coverage models and covergroups
- Run simulations, analyze results, and debug issues
- Review verification outcomes to support tape-out sign-off
- Collaborate closely with design, test, and verification stakeholders to ensure strong teamwork and effective knowledge sharing
Minimum Requirements
- MS (or BS) in Electrical/Computer Engineering or a related field with 5+ (or 8+) years of semiconductor verification experience
- Strong written and verbal English communication skills
- Proficiency in SystemVerilog and object-oriented programming concepts
- Hands-on experience with UVM-based verification methodologies
- Strong experience developing SystemVerilog Assertions (SVA)
- Proficiency with scripting languages such as Python or Perl
- Ability to read analog schematics and practical experience with Cadence Virtuoso
- Working knowledge of digital design using Verilog
- Experience collaborating with globally distributed mixed-signal, digital, and analog engineering teams
- Self-driven, with the ability to work independently and solve complex technical challenges
Desired Qualifications
- Experience modeling analog functional behavior using SystemVerilog RNM, wreal (Verilog-AMS), or similar approaches
- Familiarity with UVM-AMS methodologies
- Strong background in Formal Property Verification (FPV)
- Object-oriented programming experience in C++
- Experience in analog mixed-signal verification
- Solid understanding of analog design principles
- Knowledge of synthesizable digital design
- Experience verifying datapath designs, including filter implementations
- Proven ability to thrive in fast-paced, collaborative engineering environments
- Excellent written and verbal communication skills
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