Jobid=641863552204277810 (0.0152)
pQuantum Design Engineer at QuantWare, Delft. A mid-level full time position in the Research Development team, listed under hardware engineering. /ppAbout Us QuantWare is building the world’s most powerful quantum processors to solve humanity's greatest challenges. We do this with our unique VIO™ technology, the only QPU architecture that breaks the hardware barriers that have held quantum computing back, unlocking the path to MegaQubit quantum processors. With VIO, we are paving the way for the hyper-scale quantum computers that will change the world. And delivering on that vision demands people who don’t shy away from tackling the hardest challenges of our time. That’s where you come in! As a Quantum Design Engineer in our RD team, you’ll be at the heart of advancing the performance and scalability of superconducting quantum processors. You’ll lead the design of next-generation qubit chips and modular, scalable QPU architecture, working from on-chip subsystem architecture to EM simulations, frequency allocation, crosstalk management, packaging, and interconnect strategies. You’ll also design and optimise nonreciprocal superconducting circuits, such as isolators and parametric amplifiers that will drive robust, high-fidelity readout chains. These designs will enhance readout signal-to-noise ratio and stability, feeding into our next-gen readout modules and ensuring seamless coupling with the qubit layer. This role is highly collaborative: you’ll work in a tight feedback loop with experimentalists and device engineers to transform measurement insights into rapid design iterations, pushing performance, coherence, yield, and manufacturability across the full qubit stack. What you’ll be doing Design and simulate cutting-edge quantum hardware to improve performance, coherence, and scalability. Develop high-performance, manufacturable device architectures that accelerate RD cycles and increase qubit fidelity and yield. Architect and optimize the layout of nonreciprocal superconducting circuits such as parametric amplifiers, targeting robust performance under cryogenic conditions. Interpret simulation results and co /p #J-18808-Ljbffr
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