Delft University of Technology

PhD: Ultra-Low-Jitter CMOS PLL Design for Wireless – Delft University of Technology – Delft

Jobid=eabd8a5b10f1 (0.0156)

A leading technological university in the Netherlands is seeking a PhD candidate for a position focused on high-performance CMOS Phase-Locked Loop design. The role involves innovative circuit design, system modeling, and practical validation on silicon. Candidates should possess an M.Sc. in a related field, strong knowledge in analog and RF circuit design, and effective communication skills. This unique opportunity supports significant advancements in next-generation wireless communication systems, within a highly collaborative research team.
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