Jobid=625323032422456188 (0.0148)
ppAt Qblox, we are orchestrating the “brain” of the quantum computer. Our distributed control stacks allow for parallel qubit readout and nanosecond-level synchronization across massive architectures. Imagine the complexity of all-to-all connectivity for 1000 qubits, interacting with physical hardware via high-frequency analogue signals—that is the scale of the challenge our verification team faces. /p pAs we expand our RD capabilities, we are looking for a bDigital Verification Engineer /b to ensure our hardware is as reliable as the physics it controls. /p h3bThe Role /b /h3 pYou will be a key driver in our RTL verification strategy, developing robust, metric-driven testbenches at both the module and system levels. This is not a siloed role; you will act as a technical sparring partner for our Digital Design and Embedded Software teams, influencing architecture and processes by proposing improvements based on industry best practices. /p pAt Qblox, we foster a culture of ownership. You will have the opportunity to influence technical decisions at a high level and gain a deep understanding of the entire quantum control stack, learning from our in-house physics experts along the way. /p h3bWhat you will do /b /h3 ul lipbOwn the Verification: /b Autonomously develop robust, metric-driven testbenches for complex FPGA/RTL modules and full systems. /p /li lipbBridge the Disciplines: /b Collaborate closely with Digital Design and Embedded Software engineers to analyze requirements and verify technical solutions. /p /li lipbInterpret Complexity: /b Work with internal design specs and vendor documentation for FPGAs, third‑party ASICs, and software. /p /li lipbDrive Methodology: /b Proactively suggest and implement new tools, methodologies (like Cocotb), and advancements in the verification domain. /p /li lipbAnalyze Evaluate: /b Understand and interpret VHDL code to ensure effective verification coverage while maintaining a collaborative loop with designers. /p /li /ul h3bWhy Qblox? /b /h3 pWe offer a dynamic environment where engineering meets cutting‑edge physics research. You’ll be part of a highly international team that values inclusive knowledge exchange, technical ownership, and a healthy work‑life balance. /p h3bEnough about us, what about you? /b /h3 pTo thrive in this environment, you likely possess a “first‑principles” approach to problem‑solving and a drive to see complex RD projects through to completion. /p ul lipbThe Background: /b 4+ years of experience in RTL verification within an RD environment. /p /li lipbThe Technical Core: /b Expertise in verification planning and implementing self‑checking testbenches. You are fluent in SystemVerilog/UVM and have a strong grasp of Python (OOP). /p /li lipbThe Tools: /b Hands‑on experience with high‑end simulators (Cadence Xcelium, Synopsys VCS) and a solid understanding of VHDL. /p /li lipbThe Architectural Sense: /b Familiarity with processor and bus‑system architectures (e.g., AMBA AXI, Avalon). /p /li lipbThe Essentials: /b Proficiency with Git for version control and a results‑driven mindset with a high degree of accountability. /p /li lipbThe “Nice to Haves”: /b Knowledge of bCocotb and PyUVM /b is a significant plus. Experience with CI/CD (GitLab), container technologies (Docker/Podman), C/C++, or lab‑based product validation will help you hit the ground running. /p /li /ul /p #J-18808-Ljbffr
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